Design and Analysis of Low Power VLSI Full Adders and 32-bit Adders

MOSFET has become the most essential and fundamental building block of LSI circuits. In the past 40 years, the MOSFET devices' scaling increased performance, reduced size, and high-power consumption. The power consumption is high due to large leakage currents. Leakage current in nanometer regimes is becoming a significant contributor to the total power dissipation of CMOS circuits. The leakage current in CMOS depends on threshold voltage, channel length, and gate oxide thickness. As a result, the identification and building of different leakage components are essential for estimating and reducing leakage power.

Cadence tools are used to verify the leakage power reduction in adder circuits. The leakage power depends on leakage current. The leakage current depends on the subthreshold leakage current. The method adopted to minimize the subthreshold leakage current is through threshold voltage scale-up.

Scale-up of the threshold voltage applied to different full adders, namely CMOS full adder, Mirror full adder, Transmission gate full adder, Manchester full adder, and various full adders as presented in this thesis. This work designed full adders with 10 MOS transistors,13 MOS transistors, and 15 MOS transistors. Conventional CMOS requires 28 MOS transistors to implement the full adder. The number of transistors in proposed full adders is less than 50 percent of traditional CMOS full adder. The concept of threshold scale-up works for all technology nodes. This method has experimented with 45nm technology, and leakage analysis in full adders is carried out using the Cadence tool. Three different full adders are designed and compared with existing full adders and designed full adders .32-bit Adders are using different full adders. Leakage analysis is carried out in these 32-bit adders using threshold voltage scale-up. Aim of this work is to obtain 50% reduction in leakage power without changing overall delay of 32-bit adders. The overall average leakage power was reduced by 30% in a 32-bit ripple carry adder without changing overall propagation delay using ten transistors full adder. The overall average leakage power was reduced by 27% in a 32-bit carry select adder without changing the overall propagation delay using ten transistors full adders. The overall average leakage power was reduced by 31% in a 32-bit square root carry select adder without changing the overall propagation delay of 32-bit square root carry select adder using ten transistors full adder. The 10-transistor full adder has shown the least leakage current out of all the full adders.32-bit adder developed using ten transistors full adder has low average leakage power.